Modern integrated circuits have literally millions of active devices such as transistors and capacitors formed in or on a semiconductor substrate and rely upon an elaborate system of metal layers, typically comprising multi-level metal layer interconnections, in order to connect the active devices into functional circuits. An interlayer dielectric such as silicon dioxide is formed over a silicon substrate, and electrically isolates a first level of metal layers which is typically aluminum from the active devices formed in the substrate. Metalized contacts electrically couple active devices formed in the substrate to the interconnections of the first level of metal layers. In a similar manner, metal vias electrically couple interconnections of a second level of metal layers to interconnections of the first level of metal layers. Contacts and vias typically comprise a metal such as tungsten surrounded by a barrier metal such as titanium-nitride. Additional layers can be stacked to achieve the desired (multi-layer) interconnection structure.
High density multilevel interconnections require the planarization of the individual layers of the interconnection structure and very little surface topography variation. Non-planar surfaces create poor optical resolution for the photo lithographic procedures used to lay done additional layers in later processing steps. Poor optical resolution prevents the printing of high density lines required for high density circuit and interconnect structures. Another problem associated with surface topography variation pertains to the ability of subsequent metal layers to cover or span the step height. If a step height is too large there is a potential danger that open circuits will be created causing failure of the chip on which the open circuit occurs. Planar interconnect surface layers are a must in the fabrication of state-of-the-art high density multilevel integrated circuits.
Planar substrate topography may be achieved using chemical-mechanical polishing (CMP) techniques. In conventional CMP systems and methods a silicon wafer is placed face down on a rotatable surface or platen covered with a flat polishing pad onto which a coating or layer of an active slurry has been applied. A substrate carrier formed from a rigid metal or ceramic plate mounts the backside of the wafer and applies a downward force against the backside of the wafer so that the front side is pressed against the polishing pad. In some systems, the downward force is generated mechanically such as via a mechanical weight, however, frequently, the downward force is communicated to the substrate carrier via a pneumatic source such as air or other fluid pressure. A resilient layer, often referred to as an insert, such as may be provided by a polymeric material, wax, or other cushioning material may frequently be used between the wafer mounting surface on the carrier and the backside of the wafer. The downward polishing force is communicated through the insert.
A retaining ring circumscribing the periphery of the wafer carrier and the wafer centers the wafer on the carrier and keeps the wafer from slipping out from alignment with the carrier. The carrier which mounts the wafer is coupled to a spindle shaft which is rotated via coupling to a motor. The downward polishing force combined with the rotational movement of pad together with the CMP slurry facilitate the abrasive polishing and planar removal of the upper surface of a thin film or layer from the front side surface of the wafer.
These conventional systems and methods present at least two problems or limitations. A first problem is that an unequal polishing pressure distribution can develop across the surface of the wafer as it is polished either as a result of mechanical misalignments in the carrier or polishing head assembly, interaction of the wafer front side surface with the polishing pad and slurry, nonuniformity of the insert, contamination introduced between the insert and the wafer backside surface such as polishing debris, or a variety of other of sources of polishing force nonuniformity that affect the planarization of the wafer substrate.
The properties of the insert are particularly problematic. While the CMP equipment manufacturer may design and fabricate a device having great precision and process repeatability, it is frequently found that the physical characteristics of the polymeric inserts which must be replaced after some predetermined number of wafers have been processed, and varies from batch to batch. Furthermore, event within a single batch, the characteristics will vary with the amount of water absorbed by the insert. Even more troublesome, different portions of the same insert may be drier or wetter than other areas thereby introducing polishing variations across the surface of each wafer.
A second problem associated with conventional CMP systems and methods is that even to the extent that uniform or substantially uniform polishing pressure may be achieved, see for example copending U.S. patent application Ser. No. 09/261,112 filed 3 Mar. 1999 for a Chemical Mechanical Polishing Head Assembly Having Floating Wafer Carrier and Retaining Ring, and U.S. patent application Ser. No. 09/294,547 filed 19 Apr. 1999 for a Chemical Mechanical Polishing Head Having Floating Wafer Retaining Ring and Wafer Carrier With Multi-Zone Polishing Pressure Control, each of which are assigned to Mitsubishi Materials Corporation, the same assignee as the instant application, and hereby incorporated by reference. uniform polishing pressure may not always be the optimum polishing pressure profile for planarization of the wafer. This apparent paradox between the assumed desirability of a uniform polishing pressure and the need for a non-uniform polishing pressure arises from non-uniform layer deposition effects during the deposition process. To the extent that the deposited layer thickness varies in a known manner, such as the radially varying thickness that is frequently encountered, the polishing pressure may desirably be varied to compensate for the deposition irregularities.
The pressure at any point on the front side surface of the wafer is largely controlled by the local compressive modulus (hardness) and local compression of polishing pad, insert, and any other materials (desired or not) interposed between the source of the pressure and the contact point between the wafer and the polishing pad including the layers between the polishing pad and the generally hard rigid polishing table or platen. Any variation in the amount of compression of these elements results in local pressure variations at the polishing interface.
In general, all other factors being equal (e.g. same slurry composition, same effective linear speed of the wafer across the pad, etc.) the polish removal rate in chemical-mechanical polishing systems is proportional to the pressure applied between the wafer and the polishing pad in the direction perpendicular to the polishing motion. The greater the pressure, the greater the polish removal rate. Thus, nonuniform pressure distribution across the surface of the wafer tends to create a nonuniform polish rate across the surface of wafer. Nonuniform polishing can result in too much material being removed from some parts of wafer and not enough material being removed from other parts, and also cause formation of overly thin layers and/or result in insufficient planarization, both of which degrade semiconductor wafer process yield and reliability.
The nonuniform polishing may be particularly prevalent at the peripheral edge of the wafer where the sharp transition edge effects occur. In traditional approaches, a sharp transition exists between the portion of the polishing pad that is in contact with the polishing head (wafer, wafer carrier, and retaining ring where present) and that portion that is not in contact. Recall that conventional polishing pads are at least somewhat compressible and may be locally compressed, stretched, and deformed in the vicinity of the moving edge of the polishing head as it moves over the surface during polishing. This localized compression, stretching, and other deformation causes a localized variation in the pressure profile proximate the edge of the wafer substrate. This variation is particularly prevalent from the edge of the wafer radially inward for a centimeter or so, but particularly troublesome from the edge inward to about 3 mm to about 5 mm or so.
One solution to reducing this edge variation has been proposed in co-pending U.S. patent application Ser. No. 09/294,547 filed 19 Apr. 1999 and entitled Chemical Mechanical Polishing Head Having Floating Wafer Retaining Ring and Wafer Carrier With Multi-Zone Polishing Pressure Control; and which is hereby incorporated by reference. This patent application describes a novel retaining ring structure that minimizes the amount of pressure variation on the wafer by using a circumscribing retaining ring having a special shape profile.
Now and increasingly in the future, sub-micron integrated circuits (ICs) require that the device surfaced be planarized at their metal inter-connect steps, and chemical mechanical polishing (CMP) is the preferred wafer planarization process. Precise and accurate planarization will become increasingly important as the number of transistors and the required number of interconnections per chip increases.
Integrated circuits are conventionally formed on substrates, particularly silicon wafers, by the sequential deposition of one or more layers, which layers may be conductive, insulative, or semiconductive. These structures are sometimes referred to as the multi-layer metal structures (MIM's) and are important relative to achieving close-packing of circuit elements on the chip with the ever decreasing design rules.
Flat panel displays such as those used in notebook computers, personal data assistants (PDAs), cellular telephones, and other electronic devices, may typically deposit one or more layers on a glass or other transparent substrate to form the display elements such as active or passive LCD circuitry. After each layer is deposited, the layer is etched to remove material from selected regions to create circuitry features. As a series of layers are deposited and etched, the outer or topmost surface of the substrate becomes successively less planar because the distance between the outer surface and the underlying substrate is greatest in regions of the substrate where the least etching has occurred, and the distance between the outer surface and the underlying substrate is least in regions where the greatest etching has occurred. Even for a single layer, the non-planar surface takes on an uneven profile of peaks and valleys. With a plurality of patterned layers, the difference in the height between the peaks and valleys becomes much more severe, and may typically vary by several microns.
A non-planar upper surface is problematic respective of surface photolithography used to pattern the surface, and respective of layers that may fracture if deposited on a surface having excessive height variation. Therefore, there is a need to planarize the substrate surface periodically to provide a planar layer surface. Planarization removes the non-planar outer surface to form a relatively flat, smooth surface and involves polishing away the conductive, semiconductive, or insulative material. Following planarization, additional layers may be deposited on the exposed outer surface to form additional structures including interconnect lines between structures, or the upper layer may be etched to form vias to structures beneath the exposed surface. Polishing generally and chemical mechanical polishing (CMP) more particularly are known methods for surface planarization.
The polishing process is designed to achieve a particular surface finish (roughness or smoothness) and a flatness (freedom from large scale typography). Failure to provide minimum finish and flatness may result in defective substrates, which in tern may result in defective integrated circuits.
During CMP, a substrate such as a semiconductor wafer, is typically mounted with the surface to be polished exposed, on a wafer carrier which is part of or attached to a polishing head. The mounted substrate is then placed against a rotating polishing pad disposed on a base portion of the polishing machine. The polishing pad is typically oriented such that it's flat polishing surface is horizontal to provide for even distribution of polishing slurry and interaction with the substrate face in parallel opposition to the pad. Horizontal orientation of the pad surface (the pad surface normal is vertical) is also desirable as it permits the wafer to contact the pad at least partially under the influence of gravity, and at the very least interact in such manner that the gravitational force is not unevenly applied between the wafer and the polishing pad. In addition to the pad rotation, the carrier head may rotate to provide additional motion between the substrate and polishing pad surface. The polishing slurry, typically including an abrasive suspended in a liquid and for CMP at least one chemically-reactive agent, may be applied to the polishing pad to provide an abrasive polishing mixture, and for CMP an abrasive and chemically reactive mixture at the pad substrate interface. Various polishing pads, polishing slurries, and reactive mixtures are known in the art, and which is combination allow particular finish and flatness characteristics to be achieved. Relative speed between the polishing pad and the substrate, total polishing time, and the pressure applied during polishing, in addition to other factors influence the surface flatness and finish, as well as the uniformity. It is also desirable that the polishing of successive substrates, or where a multiple head polisher is used, all substrates polished during any particular polishing operation are planarized to the same extent, including remove of substantially the same amount of material and providing the same flatness and finish. CMP and wafer polishing generally are well known in the art and not described in further detail here.
The condition of the polishing pad may also affect polishing results, particularly the uniformity and stability of the polishing operation over the course of a single polishing run, and more especially, the uniformity of polishing during successive polishing operations. Typically, the polishing pad may become glazed during one or more polishing operations as the result of heat, pressure, and slurry or substrate clogging. The effect is to lessen the abrasive characteristic of the pad over time as peaks of the pad are compressed or abraded and pits or voids within the pad fill with polishing debris. In order to counter these effects, the polishing pad surface must be conditioned in order to restore the desired abrasive state of the pad. Such conditioning may typically be carried out by a separate operation performed periodically on the pad to maintain its abrasive state. This also assists in maintaining stable operation during which a predetermined duration of polishing will remove a predetermined amount of material from the substrate, achieve a predetermined flatness and finish, and otherwise produce substrates that have sufficiently identical characteristics so that the integrated circuits fabricated from the substrates are substantially identical. For LCD display screens, the need for uniform characteristics may be even more pronounced, because unlike wafers which are cut into individual dies, a display screen which may be several inches across, will be totally unusable if even a small area is unusable due to defects.
An insert, as has conventionally been used is an inexpensive pad that is bonded to the wafer sub-carrier and is between the backside of the wafer and the carrier surface which may be a metal or ceramic surface. Variations in the mechanical characteristics of the insert typically may cause variations in the polishing results of CMP.
In U.S. Pat. No. 5,205,082 there is described a flexible diaphragm mounting of the sub-carrier having numerous advantages over earlier structures and methods, and U.S. Pat. No. 5,584,751 provides for some control of the down force on the retaining ring through the use of a flexible bladder; however, neither these patents describe structure for direct independent control of the pressure exerted at the interface of the wafer and retaining ring, or any sort of differential pressure to modify the edge polishing or planarization effects.
In view of the foregoing, there is a need for a chemical mechanical polishing apparatus which optimizes polishing throughput, flatness, and finish, while minimizing the risk of contamination or destruction of any substrate.
The inventive structure and method incorporate numerous design details and innovative elements, some of which are summarized below. The inventive structures, methods, and elements are described in the detailed description.